PIC16F871-E/L【PDF 99/143 页】IC MCU CMOS 20MHZ 2K FLSH 44PLCC

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Sheet目录3887

95页 96页 97页 98页 [99页]100页 101页 102页 103页

2003 Microchip Technology Inc.

DS30569B-page 57

PIC16F870/871

8.3

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC2/CCP1 pin is:

Driven high

Driven low

Remains unchanged

The action on the pin is based on the value of control

bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt flag bit CCP1IF is set.

FIGURE 8-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

8.3.1

CCP PIN CONFIGURATION

The user must configure the RC2/CCP1 pin as an

output by clearing the TRISC<2> bit.

8.3.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode, or Synchro-

nized Counter mode, if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

8.3.3

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen, the

CCP1 pin is not affected. The CCPIF bit is set, causing

a CCP interrupt (if enabled).

8.3.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair, and starts an A/D conversion (if A/D

module is enabled). This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

Note:

Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to

the default low level. This is not the

PORTC I/O data latch.

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set Flag bit CCP1IF

(PIR1<2>)

Match

RC2/CCP1

TRISC<2>

CCP1CON<3:0>

Mode Select

Output Enable

Special event trigger will:

reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>).

Note:

The special event trigger from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

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